Electronic device with serial ATA interface and power saving method for serial ATA buses

ABSTRACT

In an electronic device with a serial ATA interface, upon detection of the issue or reception of a preset command, a confirmation device, such as a CPU, confirms the completion of execution of the command. Upon confirming the completion of execution of the command, a controller, which may also be the CPU, controls shifting of the serial ATA interface to a power saving mode.

CROSS REFERENCE TO RELATED APPLICATIONS

This is a divisional reissue application of U.S. patent application Ser.No. 15/160,846, filed May 20, 2016, which is a reissue application ofU.S. Pat. No. 8,732,502, issued on May 20, 2014, from U.S. patentapplication Ser. No. 12/879,332, which is This application is acontinuation of U.S. patent application Ser. No. 12/398,530, filed onMar. 5, 2009, which is a divisional of U.S. patent application Ser. No.11/956,996, filed Dec. 14, 2007, which is a divisional of U.S. patentapplication Ser. No. 10/931,949, filed Sep. 1 2004, which is based uponand claims the benefit of priority from prior Japanese PatentApplication No. 2003-310361, filed Sep. 2, 2003,. the The entirecontents of which the above-identified applications are incorporatedherein by reference.

Notice: More than one reissue application has been filed for the reissueof U.S. Pat. No. 8,732,502 B2. The reissue applications are applicationSer. No. 15/837,317 (the present application) filed on Dec. 11, 2017,and Ser. No. 15/160,846 filed on May 20, 2016 now issued as RE 47,050).Both applications are reissues of U.S. Pat. No. 8,732,502 B2.

BACKGROUND OF THE INVENTION

1. Field of the Invention

The present invention relates to an electronic device with a serial ATattachment (ATA) interface, and more particularly to an electronicdevice represented by a disk drive, and a power saving method for serialATA buses, which are suitable for reducing the power consumption of aserial ATA bus that conforms to the serial interface ATA standards.

2. Description of the Related Art

As recited in “Serial ATA: High Speed Serialized AT Attachment” Revision1.0a, Serial ATA Workgroup, Jan. 7, 2003 (hereinafter referred to as“the prior art document”), standards for serial ATA interfaces that arenew interfaces for disk drives have been worked out. Serial ATAinterfaces are used as interfaces between a peripheral device,represented by a magnetic disk drive, and a host (host system)represented by a personal computer. In this point, serial ATA interfacesare similar to conventional ATA interfaces (i.e., parallel ATAinterfaces).

A peripheral device with a serial ATA interface, such as a magnetic diskdrive (hereinafter referred to as an “HDD”), is connected to a host by aserial bus. In such an HDD, to secure compatibility with an ATAinterface, it is necessary to convert an ATA interface into a serial ATAinterface, and convert a serial ATA interface into an ATA interface.Such interface conversion is performed by, for example, an LSI (bridgeLSI) called a serial ATA bridge.

In the serial ATA interface standards, three layers of differentfunctions, i.e., a physical layer, link layer and transport layer, aredefined. The physical layer has a function for executing high-rateserial data transmission and reception. The physical layer interpretsreceived data, and transmits the data to the link layer in accordancewith an interpretation result. The physical layer also outputs a serialdata signal to the link layer in response to a request therefrom. Thelink layer supplies the physical layer with a request to output asignal. The link layer also supplies the transport layer with the datatransmitted from the physical layer. The transport layer performsconversion for operations based on the ATA standards. Assuming that theabove-mentioned bridge LSI is used in an HDD, the role of the transportlayer corresponds to the role of the ATA signal output unit of aconventional host that utilizes an ATA connection. The bridge LSI isconnected to the disk controller (HDC) of the HDD via an ATA bus (or abus compliant with the ATA bus) based on the ATA interface standards.Accordingly, in the connection between the bridge LSI and HDC of theHDD, operations equivalent to those stipulated in the ATA interfacestandards or compatible with the standards are performed. In this case,the portion of the HDD excluding the bridge LSI (hereinafter referred toas a “main HDD unit”) regards the bridge LSI as an apparatus (host) forissuing a command to the main HDD unit. Accordingly, the main HDD unitoperates in the same manner as a conventional HDD utilizing an ATAconnection. Thus, the serial ATA interface has compatibility with theATA standards concerning protocols such as logical commands. However, adata signal (parallel data signal) processed by a parallel ATA interfacemust be converted into a serial data signal.

The serial ATA interface standards stipulate a power saving modedirected to serial ATA buses, as well as a power saving mode thatconforms to the conventional ATA interface (parallel ATA interface)standards. The idea of serial ATA bus power saving does not exist in theconventional ATA standards.

The serial ATA interface standards stipulate three power managementmodes for serial ATA interfaces, i.e., “PHY READY (IDLE)”, “PARTIAL” and“SLUMBER”. The “PHY READY” mode indicates a state in which both thecircuit (PHY circuit) for realizing the operation of a physical layer(PHY layer), and the main phase-locked loop (PLL) circuit are operating,thereby synchronizing the interfacing states of the host and peripheraldevice. The “PARTIAL” mode and “SLUMBER” mode indicate a state in whichthe PHY circuit is operating but the interface signal is in a neutralstate.

The difference by definition between the “PARTIAL” mode and “SLUMBER”mode lies in the time required for restoration therefrom to the “PHYREADY (IDLE)” mode. More specifically, it is stipulated that the timerequired for restoration from the “PARTIAL” mode must not exceed 10 μs.On the other hand, it is stipulated that the time required forrestoration from the “SLUMBER” mode must not exceed 10 ms. As long asthe restoration time and interface power state conform to the standards,manufacturers can select the portion of a device, the power savingfunction of which should be executed in the “PARTIAL” mode or “SLUMBER”mode (i.e., can select the circuit that should be turned off in themode).

Shift to a power saving (ATA power saving) state conforming to theconventional ATA interface standards is realized basically under thecontrol of a host. As ATA power saving modes, “IDLE”, “STANDBY” and“SLEEP” modes, for example, are stipulated. On the other hand, shift toa power saving (serial ATA power saving) mode (i.e., the “PARTIAL” or“SLUMBER” mode) for serial ATA buses may be realized under the controlof either a host or peripheral device. However, the above-mentionedprior art document describes nothing about a technique for controllingthe serial ATA power saving state (in particular, a technique forassociating the ATA power saving state with the serial ATA power savingstate).

Assume here that a serial ATA interface is used as the interface of anHDD, and the HDD is connected to a host via a serial ATA bus. In thiscase, it is necessary, as stated above, to provide a serial ATAinterface control circuit (serial ATA bridge) for converting aconventional ATA interface (parallel ATA interface) into a serial ATAinterface. In this HDD, the operation of a junction between the serialATA interface control circuit and the hard disk controller (HDC) of theHDD is identical to or conforms to that stipulated in the conventionalATA interface standards. Accordingly, the HDC recognizes the serial ATAbridge as if it were a host itself that issues commands. This means thatthe operations of the portions of the HDD other than the serial ATAbridge peripheral portions are similar to the conventional ones. In HDDswith serial ATA interfaces, a conventional ATA bus (i.e., parallel ATAbus) that connects a serial ATA interface control circuit to an HDC canbe formed on the printed circuit board (PCB) of the HDD. Therefore, inHDDs with serial ATA interfaces, the wiring length of the ATA bus can beshortened, and hence an increase in data transfer rate, which is hard torealize if a parallel ATA bus is used, can be expected.

The serial ATA interface standards have been worked out on theassumption that they are compatible with the conventional ATA standards(parallel ATA standards). Therefore, to realize the new idea of powersaving stipulated in the serial ATA standards, it is necessary toprovide a host with new means for designating new power saving. However,such new means may well deviate from the conventional ATA standards.Further, the provision of new means to a host may significantlyinfluence the entire system.

BRIEF SUMMARY OF THE INVENTION

In an embodiment of the invention, power consumption is reduced byeffectively utilizing the power saving mode for serial ATA busesstipulated in the serial ATA standards.

In accordance with an embodiment of the invention, there is provided anelectronic device with a serial ATA interface having a detector fordetecting issue or reception of a predetermined command; a confirmationdevice for confirming completion of execution of the command detected bythe detector; and a controller for controlling shifting of the serialATA interface to a power saving mode upon confirmation of the completionof the execution by the confirmation device.

In accordance with yet another embodiment of the invention, there isprovided a disk drive with a serial ATA interface connected to a hostvia a serial ATA bus. The disk drive has a reporting device forreporting, to the host, completion of execution of a command sent fromthe host to the disk drive; and a controller for controlling shift ofthe serial ATA interface to a power saving mode after the reportingdevice reports completion of execution of a preset command.

Yet further embodiments of the invention relates to a method of savingpower of a serial ATA interface employed in an electronic device. Themethod detects issue or reception of a preset command; confirmscompletion of execution of the detected command; and shifts the serialATA interface to a power saving mode upon confirming the completion ofexecution of the detected command.

Another embodiment of the invention pertains to a method of performinginterface conversion between a serial ATA interface and a parallel ATAinterface. This method measures a preset time starting each time theserial ATA interface is shifted to an idle mode in accordance withreception of a command which requires interface conversion; and shiftsthe serial ATA interface from the idle mode to a predetermined powersaving mode if no further command has been sent after expiration of thepreset time.

Yet another embodiment of the invention involves a method for savingpower in a disk drive with a serial ATA interface connected to a hostvia a serial ATA bus. The method reports to the host completion ofexecution of a command sent from the host to the disk drive; andcontrols shifting of the serial ATA interface to a power saving modeafter the reporting device reports completion of execution of a presetcommand.

BRIEF DESCRIPTION OF THE SEVERAL VIEWS OF THE DRAWING

The accompanying drawings, which are incorporated in and constitute apart of the specification, illustrate embodiments of the invention, andtogether with the general description given above and the detaileddescription of the embodiments given below, serve to explain theprinciples of the invention.

FIG. 1 is a block diagram illustrating the configuration of a system,equipped with a magnetic disk drive (HDD) 10, according to an embodimentof the invention;

FIG. 2 is a block diagram illustrating a main HDD unit 11 incorporatedin the HDD 10 appearing in FIG. 1;

FIG. 3 is a view illustrating shift of ATA power saving modes employedin the embodiment;

FIG. 4 is a view illustrating the relationship between each ATA powersaving mode in FIG. 3 and the turned-off state of each circuit of an HDDmain unit 11 in each ATA power saving mode;

FIG. 5 is a view illustrating examples of times required forrestoration, to a read/write mode M0, from each ATA power saving mode M1to M5 in FIG. 3;

FIG. 6 is a view illustrating the relationship between each ATA powersaving mode in FIG. 3 and the corresponding SATA (serial ATA) powersaving mode set when the HDD 10 is in each ATA power saving mode;

FIG. 7 is a flowchart useful in explaining power control performed whenthe main HDD unit 11 of the HDD 10 has received a command from a host20; and

FIG. 8 is a view illustrating shift of SATA power saving modes employedin a modification of the embodiment.

DETAILED DESCRIPTION OF THE INVENTION

An embodiment in which the invention is applied to a system equippedwith a magnetic disk drive having a serial ATA (SATA) interface will bedescribed in detail with reference to the accompanying drawings. FIG. 1is a block diagram illustrating the configuration of the system equippedwith the magnetic disk drive (HDD) 10, according to the embodiment ofthe invention. As shown, the HDD 10 comprises a main HDD unit 11 andSATA interface control circuit 12. The main HDD unit 11 corresponds to aconventional HDD for performing parallel data transfer using an ATAinterface. The SATA interface control circuit 12 is a SATA (serial ATA)bridge for peripheral devices. The SATA interface control circuit 12 isconnected to a host (host system) 20 via an SATA bus (serial ATA bus)30. The SATA interface control circuit 12 is used to perform interfaceconversion between an ATA interface and SATA interface, and is formedof, for example, a large-scale integrated circuit (LSI). The SATAinterface control circuit 12 has, in particular, a function forconverting an instruction, sent via the SATA bus 30, into an instructionsuitable for an ATA bus 13 (ATA interface), and sending it to the mainHDD unit 11 via the ATA bus 13.

The host 20 is an electronic device, such as a personal computer, whichuses the HDD 10 as storage. The host 20 comprises a main host unit 21and SATA interface control circuit 22. The main host unit 21 correspondsto a conventional host for performing parallel data transfer using anATA interface. The SATA interface control circuit 22 is a host bridge,and is connected to the main host unit 21 via an ATA bus (parallel ATAbus) 23, and to the HDD 10 via the SATA bus (serial ATA bus) 30. TheSATA interface control circuit 22 is formed of an LSI for performinginterface conversion between an ATA interface and an SATA interface,like the SATA interface control unit 12 of the HDD 10. The SATAinterface control circuit 22 has, in particular, a function forconverting an instruction, sent via the SATA bus 30, into an instructionsuitable for the SATA bus 30 (SATA interface), and sending it to the HDD10 via the SATA bus 30.

The SATA interface control circuits 12 and 22 have physical layerprocessing units 121 and 221 and link/transport layer processing units122 and 222, respectively. The physical layer processing units 121 and221 execute high-rate serial data transfer (transmission/reception) viathe SATA bus 30. At this time, the data transfer rate is 1.5 Gbps(gigabits per second). The physical layer processing units 121 and 221interpret data received from the SATA bus 30, and transmits the data tothe link/transport layer processing units 122 and 222 in accordance withthe interpretation results, respectively. Further, the physical layerprocessing units 121 and 221 transmit respective serial data signals inresponse to requests from the link/transport layer processing units 122and 222, respectively. The link/transport layer processing units 122 and222 each include a link layer processing unit and transport layerprocessing unit, which are not shown. The respective link layerprocessing units of the link/transport layer processing units 122 and222 supply the physical layer processing units 121 and 221 with requeststo output signals, in response to requests from the transport layerprocessing units of the processing units 122 and 222. Further, therespective link layer processing units of the processing units 122 and222 supply the respective transport layer processing units with datatransmitted from the physical layer processing units 121 and 221. Thetransport layer processing units perform interface conversion betweenthe ATA interface and SATA interface.

Buses, such as peripheral component interconnect (PCI) buses, compatiblewith the ATA buses 13 and 23 may be employed instead of the ATA buses 13and 23. In this case, the SATA interface control circuits 12 and 22 canbe provided in a PCI bridge. Further, it is sufficient if the SATAinterface control circuits 12 and 22 (SATA bridges) have a function fortransmitting and receiving serial ATA interface signals to and from theSATA bus 30.

FIG. 2 is a block diagram illustrating the configuration of the main HDDunit 11. The main HDD unit 11 has a disk 111 as a recording medium. Atleast one surface of the disk 111 is a recording surface on which datais magnetically recorded. A head (magnetic head) 112 opposes the atleast one recording surface of the disk 111. FIG. 2 shows a case wherethe main HDD unit 11 (HDD 10) includes only one head 112, forfacilitating the drawing of the figure. However, in general, bothsurfaces of the disk 111 serve as recording surfaces, which respectiveheads oppose. Further, in the example of FIG. 2, it is assumed that themain HDD unit 11 (HDD 10) includes a single disk 111. However, it mayinclude a plurality of disks 111 stacked on each other.

The disk 111 is spun at high speed by a spindle motor (SPM) 113. Thehead 112 is used to read and write data from and to the disk 111. Thehead 112 is attached to the tip of an actuator 114. The actuator 114 hasa voice coil motor (VCM) 115. The actuator 114 is driven by the VCM 115,thereby radially moving the head 112 over the disk 111. As a result, thehead 112 is positioned on a target track. The SPM 113 and VCM 115 arepowered by respective driving currents (SPM current and VCM current)supplied from a motor driver IC 116. The motor driver IC 116 suppliesthe SPM 113 with an SPM current designated by a CPU 130, and suppliesthe VCM 115 with a VCM current designated by the CPU 130.

The head 112 is connected to a head IC (head amplifier circuit) 117. Thehead IC 117 includes a read amplifier for amplifying a read signal readby the head 112, and a write amplifier for converting write data into awrite current. The head IC 117 is connected to a read/write IC(read/write channel) 118. The read/write IC 118 is a signal processingdevice for performing various kinds of signal processing such asanalog-to-digital conversion of a read signal, encoding of write data,decoding of read data, etc. The read/write IC 118 is connected to a harddisk controller (HDC) 119.

The HDC 119 has a disk control function for controlling data transferfrom and to the disk 111. The HDC 119 includes an ATA interface. Thatis, the HDC 119 has an ATA interface control function for receiving andtransmitting commands (such as read/write commands) and data from and tothe host 20 via the ATA bus 13. However, in the embodiment that includesthe HDD 10 having a SATA interface, the HDC 119 is connected to the SATAinterface control circuit 12 via the ATA bus 13, which differs fromconventional HDDs. The HDC 119 is connected to the host 20 via the SATAinterface control circuit 12 and SATA bus 30. The HDC 119 has a buffercontrol function for controlling a buffer RAM 120. The HDC 119 includesa status register 119a used for reporting the state of the HDD 10 to thehost 20.

A part of the memory area of the buffer RAM 120 is used as a data bufferarea for temporarily storing data transferred between the host 20 andthe HDC 119 of the HDD 10. Another part of the memory area of the bufferRAM 120 is used as a flag storage area 120a for storing a flag Fdescribed later, and as a command reception time storage area 120b forstoring time information indicating the time at which a command has beenreceived. The area 120b is used as a ring buffer for storing timeinformation indicating the points in time at which a predeterminednumber of most recent commands have been received.

The CPU 130 is a main controller in the main HDD unit 11 (HDD 10). TheCPU 130 includes a nonvolatile memory (not shown) that prestores acontrol program (e.g., a flash ROM as a programmable nonvolatilememory). The CPU 130 controls each element in the HDD 10 in accordancewith the control program prestored in the nonvolatile memory. If the HDC119 receives, from the host 20, a particular command for designating apower saving mode for the ATA interface (ATA power saving mode), the CPU130 sets the HDD 10 to the ATA power saving mode designated by thecommand. When setting the ATA power saving mode, the CPU 130 causes, viathe HDC 119 and SATA bus 13, the SATA interface control circuit 12 toset a SATA power saving mode related in advance to the ATA power savingmode.

FIG. 3 is a view illustrating shift of ATA power saving modes (powersaving modes that conform to the ATA interface standards) employed inthe embodiment. In the embodiment, ATA power saving modes include fivemodes—ACTIVE IDLE MODE M1, PERFORMANCE IDLE MODE M2, LOWER-POWER IDLEMODE M3, STANDBY MODE M4 and SLEEP MODE M5. In addition to the powersaving modes M1 to M5, READ/WRITE MODE (ACTIVE MODE) M0 is provided asanother ATA interface mode for enabling a read/write command to beexecuted. The power consumption is reduced in the order of theREAD/WRITE MODE M0, ACTIVE IDLE MODE M1, PERFORMANCE IDLE MODE M2,LOW-POWER IDLE MODE M3, STANDBY MODE M4 and SLEEP MODE M5.

In the HDD 10 (main HDD unit 11), after a read/write operation commandedby a read/write command is performed in the READ/WRITE MODE M0, the HDD10 is shifted to the ACTIVE MODE M1 under the control of the CPU 130 forreducing the power consumption of the HDD 10. If no further command hasbeen sent from the host 20 after a predetermined time T1 elapses fromthe shift to the ACTIVE IDLE MODE M1, the HDD 10 is autonomously shiftedto the PERFORMANCE IDLE MODE M2 under the control of the CPU 130 tofurther reduce the power consumption of the HDD 10. The Modes M1 and M2are ATA power saving modes arbitrarily designated by a manufacturer.

If no further command has been sent from the host 20 after apredetermined time T2 elapses from the shift to the PERFORMANCE IDLEMODE M2, the HDD 10 is autonomously shifted to the LOW-POWER IDLE MODEM3 under the control of the CPU 130 to further reduce the powerconsumption of the HDD 10. The Mode M3 corresponds to “IDLE” in the ATAinterface standards. Accordingly, if an idle command is sent from thehost 20 in the mode M1 or M2, the ATA power saving mode of the HDD 10 isshifted to the LOW-POWER IDLE MODE M3 in accordance with the command.Similarly, if a standby command is sent from the host 20 in the mode M1,M2 or M3, the ATA power saving mode of the HDD 10 is shifted to theSTANDBY MODE M4 in accordance with the command Standby Immediate Commandis known as a kind of standby command. Using this command, the timerequired for the shift to the standby mode can be designated. Uponissuing the Standby Immediate Command, the mode is shifted to theSTANDBY MODE M4 after the designated time elapses. Further, if a sleepcommand is sent from the host 20 in the mode M1, M2, M3 or M4, the ATApower saving mode of the HDD 10 is shifted to the SLEEP MODE M5 inaccordance with the command If a read/write command is sent from thehost 20 in the mode M1, M2, M3, M4 or M5, the ATA power saving mode ofthe HDD 10 is shifted to the READ/WRITE MODE M0 in accordance with thecommand.

FIG. 4 shows the relationship between each mode M0 to M5 in FIG. 3 andthe turned-off state of each circuit of the HDD main unit 11 in eachmode M0 to M5. In the READ/WRITE MODE M0, power is supplied to eachcircuit in the main HDD unit 11 so that read and write operations can beperformed simultaneously in the main HDD unit 11. In each of the ACTIVEIDLE MODE M1, PERFORMANCE IDLE MODE M2 and LOW-POWER IDLE MODE M3, thesupply of power to part of the circuits in the main HDD unit 11 ishalted. In the ACTIVE IDLE MODE M1, the disk 111 is rotated by the SPM113 and the head 112 is positioned, by servo control, on a certain trackof the disk 111. In the PERFORMANCE IDLE MODE M2, the disk 111 isrotated by the SPM 113 and the head 112 is positioned on an arbitrarytrack without servo control. In the LOW-POWER IDLE MODE M3, although thedisk 111 is rotated by the SPM 113, the head 112 is retracted from thedisk 111. Accordingly, in the ACTIVE IDLE MODE M1, only the supply ofpower to part (i.e., a write channel) of the read/write IC 118 ishalted. On the other hand, in the PERFORMANCE IDLE MODE M2, the supplyof power to part (i.e., a VCM driver) of the motor driver IC 116 andpart of the read/write IC 118 is halted. Further, in the LOW-POWER IDLEMODE M3, the supply of power to part of the motor driver IC 116 ishalted, and the supply of power to the head IC 117 and read/write IC 118is halted. The time required until the read/write mode M0 is restored(i.e., the restoration time required until the read/write operationsbecome able to be re-executed) differs between the above-mentioned idlemodes. This restoration time is set longer in the order of the ACTIVEIDLE MODE M1, PERFORMANCE IDLE MODE M2 and LOW-POWER IDLE MODE M3. Therequired power consumption is lower in the order of the ACTIVE IDLE MODEM1, PERFORMANCE IDLE MODE M2 and LOW-POWER IDLE MODE M3. In other words,the longer the restoration time, the lower the power consumption.

In the STANDBY MODE M4, the rotation of the SPM 113 is stopped. In thismode, the supply of power to the SPM 113, motor driver IC 116, head IC117, read/write IC 118 and buffer RAM 120 is halted. Accordingly, thepower consumption is lower in the STANDBY MODE M4 than in the LOW-POWERIDLE MODE M3, whereas the restoration time is longer in the former thanin the latter. In the SLEEP MODE M5, power is supplied only to part(i.e., a reset processing circuit) of the HDC 119, the supply of powerto the other circuits being halted. Restoration from the SLEEP MODE M5to the READ/WRITE MODE M0 can be realized only by a reset operation, andthe required restoration time is almost equal to that required forrestoration from the STANDBY MODE M4. Of the modes M0 to M5, the powerconsumption is minimum in the SLEEP MODE M5.

FIG. 5 shows examples of times required for restoration from each modeM1 to M5 to the read/write mode M0. FIG. 6 shows the relationshipbetween each mode M0 to M5 and the corresponding SATA power saving modeset by the CPU 130 when the HDD 10 is in each mode M0 to M5. In theexample of FIG. 6, when the ATA power saving mode (ATA interface mode)is the READ/WRITE MODE M0, the SATA power saving mode (SATA interfacemode) is set to IDLE MODE M11. Further, when the ATA power saving modeis the ACTIVE IDLE MODE M1 or PERFORMANCE IDLE MODE M2, the SATA powersaving mode is set to PARTIAL MODE M12. However, since the PERFORMANCEIDLE MODE M2 is set only after the ACTIVE IDLE MODE M1, the PARTIAL MODEM12 is maintained when the HDD 10 is shifted to the PERFORMANCE IDLEMODE M2. Further, when the ATA power saving mode is the LOW-POWER IDLEMODE M3, STANDBY MODE M4 or SLEEP MODE M5, the SATA power saving mode isset to SLUMBER MODE M13.

Referring now to the flowchart of FIG. 7, an operation of the systemshown in FIG. 1 will be described, using, as an example, power controlexecuted when the main HDD unit 11 of the HDD 10 has received a commandfrom the host 20.

Assume here that the main host unit 21 of the host 20 has issued, to theATA bus 23, an HDD-directed command that conforms to the ATA interfacestandards. The command on the ATA bus 23 is received by the SATAinterface control circuit 22 of the host 20. The link/transport layerprocessing unit 222 of the SATA interface control circuit 22 convertsthe received command into a command conforming to the SATA interfacestandards (i.e., into a command suitable for the SATA bus 30), and sendsit to the SATA bus 30. The command on the SATA bus 30 is received by theSATA interface control circuit 12 of the HDD 10. The link/transportlayer processing unit 122 of the SATA interface control circuit 12converts the received command into a command conforming to the ATAinterface standards (i.e., into a command suitable for the ATA bus 13),and sends it to the ATA bus 13. The command on the ATA bus 13 isreceived by the HDC 119 incorporated in the main HDD unit 11 of the HDD10. The HDC 119 recognizes the SATA interface control circuit 12 as ahost. The command received by the HDC 119 is transferred to the CPU 130.

Upon receiving the command from the HDC 119, the CPU 130 stores, intothe command reception time storage area 120b, command reception timeinformation indicating the time at which the command was received (stepS1). Subsequently, the CPU 130 determines whether the received commandis one of the preset commands (step S2). The preset commands indicatecommands related to power saving, such as an idle command, standbycommand and sleep command.

If the received command is one of the preset commands, the CPU 130performs the following processing. Firstly, the CPU 130 interprets thereceived command and executes the operation indicated by the command(step S3). Specifically, if the received command is an idle command, theCPU 130 shifts the ATA power saving mode of the HDD 10 to the LOW-POWERIDLE MODE M3. Further, if the received command is a standby command, theCPU 130 shifts the ATA power saving mode of the HDD 10 to the STANDBYMODE M4. If the received command is a sleep command, the CPU 130 shiftsthe ATA power saving mode of the HDD 10 to the SLEEP MODE M5.

Upon completing the execution of the command and confirming thecompletion, the CPU 130 executes processing for reporting the completionof the execution of the command to the host 20 (step S4). Specifically,the CPU 130 sets, in the status register 119a, a response statusindicating the completion of the execution of the command, and sends aninterrupt signal to the ATA bus 13. The SATA interface control circuit12 reads the contents of the status register 119a in response to theinterrupt signal. Based on the read contents of the status register119a, the SATA interface control circuit 12 sends, to the host 20 viathe SATA bus 30, a report of the completion of a command (hereinafterreferred to as a “command execution completion report”), the reportconforming to the SATA interface standards. Upon receiving the commandexecution completion report from the SATA bus 30, the SATA interfacecontrol circuit 22 of the host 20 sends an interrupt signal to the mainhost unit 21 via the ATA bus 23. In response to the interrupt signal,the main host unit 21 receives the command execution completion report(i.e., a response indicating the completion of the command, which willhereinafter be referred to as a “command completion response”) from theSATA interface control circuit 22.

In the embodiment, if the command sent from the host 20 to the HDD 10 isone of the preset commands, i.e., one of the commands related to powersaving, the CPU 130 performs SATA power saving mode control on the SATAinterface control circuit 12 (i.e., power control for the SATA bus 30).In this control, if the command is an idle command, standby command orsleep command, the SATA power saving mode is shifted to the SLUMBER MODEM13. As a result, the serial ATA power saving function stipulated in theserial ATA standards can be effectively utilized to reduce the powerconsumption, with the compatibility with the conventional ATA standardsmaintained.

The control of the SATA power saving mode by the CPU 130 is achieved bysending a particular primitive to the link/transport layer processingunit 122 (link layer processing unit) of the SATA interface controlcircuit 12 via the ATA bus 13. The particular primitive contains asignal pattern for designating a SATA power saving mode that conforms tothe SATA interface standards. The SATA interface control circuit 12 mayinclude a control register for SATA power saving mode control. In thiscase, the SATA bus 30 can be set to a target SATA power saving mode bycontrolling the control register by the CPU 130.

For the reason stated below, the embodiment does not employ a mechanismin which after the completion of a command related to ATA power savingis reported (i.e., after a command completion response), the SATA bus 30is immediately shifted to the corresponding SATA power saving mode. Ifthe SATA bus 30 is shifted to the SLUMBER MODE M13 immediately after thecompletion of the execution of a command is reported, and if a responseindicating the completion of a subsequent command must be issued, arestoration time of 10 ms at maximum is required until the responsebecomes able to be returned. In other words, according to the definitionof the SLUMBER MODE M13, a period of 10 ms is required at maximum whenthe SATA bus 30 is restored from the SLUMBER MODE M13 to the IDLE MODEM11. For example, assume that the host 20 issues, to the HDD 10, astandby command, for example, a standby immediate command, and thenmonitors halting of the SPM 113 using a check power mode command. Inthis case, if the SATA power saving mode is shifted to the SLUMBER MODEM13 immediately after the completion of the execution of the standbyimmediate command is reported (i.e., after a command completionresponse), the speed of a response indicating the completion of asubsequent check power mode command is inevitably reduced. In light ofthis, in the embodiment, the SATA bus 30 is not unconditionally shiftedto the SLUMBER MODE M13 immediately after a command completion response.

This will now be described in more detail. Assume here that the host 20issues a check power mode command to the HDD 10 immediately after theSATA bus 30 is shifted to the SLUMBER MODE 13 upon the completion of theexecution of a standby immediate command In this case, when the checkpower mode command is issued, the SATA bus 30 is already shifted to theSLUMBER MODE M13. To transmit a command from the host 20 to the HDC 119of the HDD 10 via the SATA bus 30, it is necessary to restore the SATAbus 30 to a command transmittable state, i.e., the IDLE MODE M11. Thatis, to transmit the check power mode command, the SATA interface controlcircuit 22 of the host 20 executes a restoration procedure. As a result,the host 20 recognizes that a response from the HDD 10 indicating thecompletion of the execution of the check power mode command is delayedby the time required for the restoration of the SATA bus 30 to the IDLEMODE M11.

The command (check power mode command) issued from the host 20 reachesthe HDD 10, after the SATA bus 30 is restored from the SLUMBER MODE M13(power saving state) to the IDLE MODE M11 in accordance with the issueof the command to thereby make the host 20 and HDD 10 accessible. Atthis time, the link/transport layer processing unit 122 (transport layerprocessing unit) of the SATA interface control circuit 12 is operated totransfer the command to the HDC 119 of the HDD 10. Thus, the commandissued from the host 20 reaches the HDC 119 of the HDD 10, delayed bythe restoration time of the SATA bus 30. However, the HDC 119 cannotrecognize the delay.

Because of this, when the SATA power saving mode is controlled, thefrequency of reception of a command is calculated (step S7). The commandreception frequency is calculated from a sequence of, for example, apredetermined number of command reception time points indicated bycommand reception time information stored in the command reception timestorage area 120b of the buffer RAM 120. The average of the commandreception intervals or the highest probable command reception intervalcan be used as the command reception frequency. Further, a sequence ofcommand reception time points within a certain time period around thepresent time point may be used instead of a sequence of a predeterminednumber of command reception time points.

From the calculated command reception frequency (command receptioninterval), the CPU 130 determines the time at which the SATA bus isshifted to the SATA power saving mode determined by the currentlyreceived command, and performs control so that the SATA power savingmode is realized at the determined time (step S8). Assume here that thecalculated command reception frequency, i.e., the command receptioninterval, is Tc. In this case, if the HDC 119 has not received asubsequent command when Tc elapses, the CPU 130 causes the SATAinterface control circuit 12 to shift the SATA bus 30 to the SATA powersaving mode determined by the currently received command As a result,control of shifting the SATA bus to the SATA power saving modedetermined by a command related to ATA power saving is delayed by Tcwhile a subsequent command is being executed. In this case, the issue ofa response indicating completion of the subsequent command, if the host20 has issued the subsequent command at this time, is prevented frombeing delayed.

It is very possible that the host 20 will issue a check power modecommand to the HDD 10 after the issue of a command related to ATA powersaving. Because of this, after the issue of a response indicating thecompletion of a command related to ATA power saving, the CPU 130 mayconfirm a halt of the SPM 113, and performs control for shifting theSATA bus to the SLUMBER MODE M13, a predetermined time period after thetime of confirmation. This control can also prevent delay of the issueof a response indicating the completion of a subsequent command.Alternatively, the shift to the SLUMBER MODE M13 may be performed apredetermined time after the latest reception of a command that does notrequire restart of the SPM 113. In the embodiment, regardless of whethera command from the host 20, related to ATA power saving, is a standbycommand or sleep command, the SATA power saving mode is set to theSLUMBER MODE M13. However, depending upon the type of command or thestructure of the SATA interface control circuit 12 (the capability ofrestoring to the IDLE MODE M111), the SATA power saving mode may be setto the PARTIAL MODE M12 from which the SATA bus can be restored to theIDLE MODE M11 in a shorter period.

In the embodiment, to reduce the power consumption of the HDD 10, theHDD 10 employs the structure as shown in FIG. 3, in which the ATA powersaving mode is autonomously shifted between the set modes, regardless ofa command, from the host 20, related to the ATA power saving.Specifically, immediately after read/write processing is finished in theread/write mode M0, the CPU 130 of the HDD 10 shifts the HDD 10 from theREAD/WRITE MODE M0 to the ACTIVE IDLE MODE M1. Further, if no furthercommand has been sent from the host 20 when a predetermined time T1elapses after the shift to the ACTIVE IDLE MODE M1, the CPU 130 shiftsthe HDD 10 from the ACTIVE IDLE MODE M1 to the PERFORMANCE IDLE MODE M2.Similarly, if no further command has been sent from the host 20 when apredetermined time T2 elapses after the shift to the PERFORMANCE IDLEMODE M2, the CPU 130 shifts the HDD 10 from the PERFORMANCE IDLE MODE M2to the LOW-POWER IDLE MODE M3. It is advisable, for example, todynamically and periodically change the times T1 and T2 based on thepreviously mentioned command reception frequency (command receptioninterval).

In the embodiment, when ATA power saving mode shift is autonomouslyperformed in the HDD 10 under the control of the CPU 130, SATA powersaving mode shift is performed in synchrony with the autonomous ATApower saving mode shift as shown in FIG. 6. Specifically, during a shiftfrom the READ/WRITE MODE M0 to the ACTIVE IDLE MODE M1, the SATA powersaving mode is shifted from the IDLE MODE M11 to the PARTIAL MODE M12.Further, during a shift from the ACTIVE IDLE MODE M1 to the PERFORMANCEIDLE MODE M2, the SATA power saving mode is maintained in the PARTIALMODE M12. During a shift from the PERFORMANCE IDLE MODE M2 to theLOW-POWER IDLE MODE M3, the SATA power saving mode is shifted from thePARTIAL MODE M12 to the SLUMBER MODE M13. In the LOW-POWER IDLE MODE M3,the head 112 is retracted from the disk 111. When the HDD 10 is in theLOW-POWER IDLE MODE M3, if the host 20 supplies the HDD 10 with aread/write command, the time required for restoration to the READ/WRITEMODE M0 is relatively long and exceeds 30 ms (see FIG. 5). In this case,it is effective to set the SATA bus 30 (SATA interface) to the SLUMBERMODE M13 as in the embodiment, in order to suppress power consumption.

Access to the HDD 10 by the host 20 is liable to be often centralized ordecentralized. For example, there is a case where no command is receivedfor a certain time after a state, in which the command receptioninterval is very short, continues. In this case, it is advisable for theCPU 130 to estimate that the host 20 has finished execution of anapplication, and to set the HDD to an ATA power saving mode in which thepower consumption is reduced in a relatively short time. Further, in acase where the command reception interval is relatively long and thisstate continues for a long time, i.e., where the HDD 10 is continuouslyaccessed for a long time, it is advisable for the CPU 130 to set an ATApower saving mode in which the time required until the power consumptionis reduced is relatively long. In both cases, the SATA power saving modeis controlled in synchronism with the ATA power saving mode.

In the embodiment, the CPU 130 of the HDD 10 controls the SATA powersaving mode (mode for saving the power of the SATA bus 30). However, theSATA interface control circuit 12 can perform this control. FIG. 8 showsshift of states when the SATA interface control circuit 12 controls theSATA power saving mode. Assume that the SATA interface control circuit12 has received a command from the host 20, whereby the SATA bus 30 isshifted (restored) to the IDLE MODE M11. If no new command has been sentfrom the host 20 when a predetermined time T4 elapses after the time ofthe shift to the IDLE MODE M11, the SATA interface control circuit 12performs control for shifting the SATA bus 30 from the IDLE MODE M11 tothe PARTIAL MODE M12. Further, if no new command has been sent from thehost 20 when the predetermined time T5 elapses after the time of theshift to the PARTIAL MODE M12, the SATA interface control circuit 12performs control for shifting the SATA bus 30 from the PARTIAL MODE M12to the SLUMBER MODE M13. The SLUMBER MODE M13 is continued until a newcommand is sent from the host 20. The predetermined times T4 and T5 maybe measured using one or more timers (time measurement means) and T4 maybe equal to T5. Alternatively, when the SATA bus is shifted from theIDLE MODE M11 to the PARTIAL MODE M12, the PARTIAL MODE M12 may becontinued until a new command is sent from the host 20. Also, the SATAbus may be directly shifted from the IDLE MODE M11 to the SLUMBER MODEM13. Furthermore, the SATA power saving mode control function may beimparted from the SATA interface control circuit 12 to the HDC 119 ofthe HDD 10.

In the embodiment, SATA power saving mode control (power saving of theSATA bus 30) is performed under the control of the HDD 10. For the SATApower saving mode control, it is necessary to make both the SATAinterface control circuit 12 of the HDD 10 and the SATA interfacecontrol circuit 22 of the host 20 support the SATA power saving mode(i.e., to make the circuits 12 and 22 support the SATA power savingfunction). If the SATA interface control circuit 22 does not support theSATA power saving mode (the PARTIAL MODE M12 or SLUMBER MODE M13), ashift to the SATA power saving mode (the PARTIAL MODE M12 or SLUMBERMODE M13) is impossible. In the description below, the fact that theSATA interface control circuit 22 does not support the SATA power savingmode is equivalent to the expression that the host 20 does not supportthe SATA power saving mode. The method for recognizing whether a SATAinterface control circuit supports the SATA power saving mode isstipulated in the SATA interface standards. The SATA interface standardsstipulate that from the mutual operations of SATA interface controlcircuits connected by a SATA bus (in the embodiment, the SATA interfacecontrol circuits 12 and 22), whether these circuits support the SATApower saving mode is recognizable. Assume here that the host 20connected to the HDD 10 via the SATA bus 30 does not support the SLUMBERMODE M13. In this case, each time an instruction to shift the SATA busto the SLUMBER MODE M13 (i.e., a primitive containing a patternindicating the instruction) is issued from the HDD 10 to the host 20,the SATA interface control circuit 22 of the host 20 returns a responseindicating that the shift to the SLUMBER MODE M13 is impossible. Thus,when the host 20 does not support the SATA power saving mode, if the HDD10 issues, to the host 20, an instruction to shift to the SATA powersaving mode, the host 20 always returns a response indicating that theshift to the SATA power saving mode is impossible. Thus, control of theSATA power saving mode in the host 20 by the HDD 10 fails. In otherwords, if the HDD 10 is connected, via the SATA bus 30, to a host 20that does not support the SATA power saving mode, it is useless for theHDD 10 to perform SATA power saving mode control.

Because of the above, in the embodiment, if the host 20 returns aresponse indicating that a shift to a designated SATA power saving modeis impossible, i.e., if SATA power saving mode control has failed, theCPU 130 of the HDD 10 sets the flag F stored in the flag storage area120a in the buffer RAM 120 (steps S9 and S10). If SATA power saving modecontrol becomes necessary on another occasion, the CPU 130 refers to thestate of the flag F to determine whether SATA power saving is possible(steps S5 and S6). If the flag F is set, the CPU 130 determines thatSATA power saving is impossible, and does not perform SATA power savingmode control (steps S7 and S8). As a result, when the SATA interfacecontrol circuit 22 of the host 20 does not support the SATA power savingmode, therefore SATA power saving mode control is useless, this uselesscontrol is prevented from being executed, thereby stabilizing theoperation of the SATA bus 30.

When both the HDD 10 and host 20 support the SATA power saving mode,SATA power saving mode control can be executed under the control of thehost 20. However, in the HDD 10, a shift to the ATA power saving mode isautonomously performed regardless of a command, from the host 20,related to ATA power saving. Accordingly, to set a SATA power savingmode suitable for the current ATA power saving mode of the HDD 10, it ismore appropriate to control the SATA power saving mode of the SATA bus30 under the control of the HDD 10 in synchronism with the ATA powersaving mode of the HDD 10, than to perform such control under thecontrol of the host 20.

The above-described embodiment is directed to a system equipped with anHDD (magnetic disk drive). However, the present invention is alsoapplicable to a system equipped with another type of disk drive, such asan optical disk drive, magneto-optical disk drive, etc. It is sufficientif the disk drive has a SATA interface. The present invention is furtherapplicable to a system equipped with an electronic device other thandisk drives, if only the electronic device has a SATA interface.

Additional advantages and modifications will readily occur to thoseskilled in the art. Therefore, the invention in its broader aspects isnot limited to the specific details and representative embodiments shownand described herein. Accordingly, various modifications may be madewithout departing from the spirit or scope of the general inventiveconcept as defined by the appended claims and their equivalents.

What is claimed is:
 1. An electronic device with a serial ATA interfaceconnectable to a host via a serial ATA bus, comprising: an executionmodule configured to execute a command which is configured to designatea portion of the electronic being output from the host, the specificpower saving mode being one of power saving modes which differ in typefrom a power saving mode for the serial ATA interface; a reportingmodule configured to report completion of execution of the command tothe host; and a control module configured to control setting of aslumber mode or a partial mode as the power saving mode for the serialATA interface after the reporting, the slumber mode or the partial modebeing related to the specific power saving mode, and wherein: thecontrol module comprises a timing module configured to determine aperiod required from the time of the reporting to the time when theslumber mode or the partial mode is set; and the control module isconfigured to control setting of the slumber mode or the partial modeafter the determined period elapses from the time of the reporting. 2.The electronic device of claim 1, wherein the timing module isconfigured to determine the period based on a frequency of reception ofa command.
 3. The electronic device of claim 2, further comprising: amemory configured to store reception time information indicating a timeat which a command is received; and a calculation module configured tocalculate the frequency of reception based on the reception timeinformation stored in the memory.
 4. The electronic device of claim 1,wherein: the command is a sleep command; and the control module isconfigured to control setting of the slumber mode for the serial ATAinterface after the reporting of the completion of the execution of thesleep command, the slumber mode being related to the specific powersaving mode.
 5. The electronic device of claim 1, wherein the controlmodule is configured to control setting of the electronic device in anidle mode and setting of the partial mode for the serial ATA interfaceafter a read/write operation commanded by a read/write command isperformed in a read/write mode, the partial mode being related to theidle mode.
 6. The electronic device of claim 1, further comprising: adetection module configured to detect that the host does not support apower saving function of the serial ATA interface, when the host returnsa response indicating that the host does not adapt to setting of thepower saving mode for the serial ATA interface, the response being madeto the control of the control module; and a storing device configured tostore flag information indicating the detection result, and wherein thecontrol module is configured (a) to refer to the flag information beforethe control, and (b) to inhibit the control if the flag informationindicates that the host does not support the power saving function ofthe serial ATA interface.
 7. The electronic device of claim 1, furthercomprising a disk drive.
 8. An information apparatus comprising: theelectronic device of claim 1; a host configured to use the electronicdevice; and a serial ATA bus configured to connect the electronic deviceand the host.
 9. A controller comprising: a reporting module configuredto report completion of execution of a command to a host, the commandbeing configured to designate a portion of an electronic device with aserial ATA interface in a specific power saving mode and being outputfrom the host, the specific power saving mode being one of power savingmodes which differ in type from a power saving mode for the serial ATAinterface, the electronic device being connectable to the host via aserial ATA bus; and a control module configured to control setting of aslumber mode or a partial mode as the power saving mode for the serialATA interface after the reporting, the slumber mode or the partial modebeing related to the specific power saving mode, and wherein: thecontrol module comprises a timing module configured to determine aperiod required from the time of the reporting to the time when theslumber mode or the partial mode is set; and the control module isconfigured to control setting of the slumber mode or the partial modeafter the determined period elapses from the time of the reporting. 10.The controller of claim 9, wherein the timing module is configured todetermine the period based on a frequency of reception of a command. 11.The controller of claim 10, further comprising: a memory configured tostore reception time information indicating a time at which a command isreceived; and a calculation module configured to calculate the frequencyof reception based on the reception time information stored in thememory.
 12. The controller of claim 9, wherein: the command is a sleepcommand; and the control module is configured to control setting of theslumber mode for the serial ATA interface after the reporting of thecompletion of the execution of the sleep command, the slumber mode beingrelated to the specific power saving mode.
 13. The controller of claim9, wherein the control module is configured to control setting of theelectronic device in an idle mode and setting of the partial mode forthe serial ATA interface after a read/write operation commanded by aread/write command is performed in a read/write mode, the partial modebeing related to the idle mode.
 14. The controller of claim 9, furthercomprising: a detection module configured to detect that the host doesnot support a power saving function of the serial ATA interface, whenthe host returns a response indicating that the host does not adapt tosetting of the power saving mode for the serial ATA interface, theresponse being made to the control of the control module; and a storingdevice configured to store flag information indicating the detectionresult, and wherein the control module is configured (a) to refer to theflag information before the control, and (b) to inhibit the control ifthe flag information indicates that the host does not support the powersaving function of the serial ATA interface.
 15. A method for savingpower in an electronic device with a serial ATA interface connectable toa host via a serial ATA bus, comprising: executing a command which isconfigured to designate a portion of the electronic device in a specificpower saving mode, the command being output from the host, the specificpower saving mode being one of power saving modes which differ in typefrom a power saving mode for the serial ATA interface; reportingcompletion of execution of the command to the host; controlling settingof a slumber mode or a partial mode as the power saving mode for theserial ATA interface after the reporting, the slumber mode or thepartial mode being related to the specific power saving mode; anddetermining a period required from the time of the reporting to the timewhen the slumber mode or the partial mode is set, and wherein theslumber mode or the partial mode is set after the determined periodelapses from the time of the reporting.
 16. The method of claim 15,wherein: the command is a sleep command; and the slumber mode for theserial ATA interface is set after the reporting of the completion of theexecution of the sleep command, the slumber mode being related to thespecific power saving mode.
 17. The method of claim 15, furthercomprising: setting the electronic device in an idle mode after aread/write operation commanded by a read/write command is performed in aread/write mode; and setting the partial mode for the serial ATAinterface when the electronic device is set in the idle mode, thepartial mode being related to the idle mode.
 18. The method of claim 15,further comprising: detecting that the host does not support a powersaving function of the serial ATA interface, when the host returns aresponse indicating that the host does not adapt to setting of the powersaving mode for the serial ATA interface, the response being made to thecontrolling; storing flag information in a storing device, the flaginformation indicating the detection result; referring to the flaginformation before the controlling; and inhibiting the controlling ifthe flag information indicates that the host does not support the powersaving function of the serial ATA interface.
 19. An electronic devicecomprising: a nonvolatile memory; and a controller; the controllercomprising a first interface circuit and a second interface circuit; thefirst interface circuit being adapted to interface with a secondelectronic device via a serial interface using a first standard for aserial ATA interface; the controller being coupled with the nonvolatilememory via the second interface circuit: wherein the controller isconfigured to: receive a first indicator from the second electronicdevice via the serial interface, the first indicator being an indicatorassociated with a second standard for an ATA interface being adapted tocause a reduction of a power consumption of the electronic device;responsive to receiving the first indicator, transmit a first responseto the second electronic device via the serial interface; and cause theserial interface of the electronic device to enter into one mode ofpower saving modes associated with the first standard, after a firsttime period following the transmission of the first response.
 20. Theelectronic device of claim 19, wherein the controller is configured to:cause the serial interface of the electronic device to transition fromthe one mode of the power save modes associated with the first standardto a second mode of the power save modes associated with the firststandard, after the transmission of the first response.
 21. Theelectronic device of claim 20, wherein the transition from the one modeof the power save modes to the second mode of the power save modes isperformed after a second time period following the transmission of thefirst response.
 22. The electronic device of claim 21, wherein aduration of the second time period relates to the transitioning from theone mode of the power save modes associated with the first standard tothe second mode of the power save modes associated with the firststandard.
 23. The electronic device of claim 20, wherein the controlleris further configured to: receive a second indicator from the secondelectronic device via the serial interface; after receiving the secondindicator, cause the electronic device to transition from the secondmode of the power save modes associated with the first standard to theone mode of the power save modes associated with the first standard,after a second time period following the receipt of the secondindicator.
 24. The electronic device of claim 23, wherein a duration ofthe second time period relates to the transitioning from the second modeof the power save modes associated with the first standard to the onemode of the power save modes associated with the first standard.
 25. Theelectronic device of claim 23, wherein the second indicator relates to acheck power command.
 26. The electronic device of claim 19, wherein thefirst indicator relates to a first power-save command.
 27. Theelectronic device of claim 26, wherein the first power-save commandcomprises at least one of: a Sleep command, an Idle command, a Standbycommand, and a Standby Immediate command under an ATA Standard; whereinthe first standard comprises a Serial ATA standard; and wherein the onemode of the power saving modes comprises Slumber Mode, Partial Mode, orIdle Mode under the Serial ATA standard.
 28. The electronic device ofclaim 27, wherein the one mode of the power saving modes comprisesSlumber Mode, Partial Mode, or Idle Mode under the Serial ATA standardif the first power-save command comprises at least one of: a Sleepcommand, an Idle command, a Standby command, and a Standby Immediatecommand under an ATA Standard.
 29. The electronic device of claim 27,wherein the electronic device enters into the one mode of the powersaving modes after the first time period following the transmission ofthe response if the first power-save command comprises at least one of:a Sleep command, an Idle command, a Standby command, and a StandbyImmediate command under an ATA Standard.
 30. The electronic deviceaccording to the claim 26, wherein the first standard comprises a SerialATA standard, the second standard comprises an ATA standard, and thefirst power-save command comprises a command under the ATA Standard. 31.The electronic device of claim 26, wherein the one mode of the powersaving modes is based on information included in the first power-savecommand.
 32. The electronic device of claim 19, wherein the process ofreceiving an indicator is repeated in response to a second indicator.33. The electronic device of claim 19, wherein the electronic devicefurther comprises a register to store the first indicator.
 34. Theelectronic device of claim 19, wherein a duration of the first timeperiod relates to a frequency of receiving a plurality of indicatorsincluding the first indicator.
 35. The electronic device of claim 19,wherein the controller is configured to: without receiving a secondindicator subsequent to the first indicator within the first timeperiod, cause the electronic device to transition from the one mode ofthe power save modes associated with the first standard to a second modeof the power save modes associated with the first standard.
 36. Theelectronic device of claim 19, wherein the controller is configured tocause the electronic device to enter into the one mode of power savingmodes associated with the first standard after the first time periodfollowing the transmission of the first response and without receivinganother indicator from the second electronic device during the firsttime period.
 37. The electronic device of claim 19, wherein thecontroller is configured to: without receiving a second indicatorassociated with the first standard and subsequent to the first indicatorwithin the first time period, cause the electronic device to transitionfrom the one mode of the power save modes associated with the firststandard to a second mode of the power save modes associated with thefirst standard.
 38. The electronic device according to the claim 19,further comprising a volatile memory to store data received from thesecond electronic device via the serial interface.
 39. The electronicdevice according to the claim 19, wherein the first standard comprises aSerial ATA standard.
 40. The electronic device according to the claim19, wherein the one mode of the power saving modes comprises a SlumberMode under a Serial ATA standard.
 41. The electronic device of claim 19,wherein the first interface circuit comprises an interface circuit thatcommunicates using a Serial ATA standard.
 42. The electronic device ofclaim 19, wherein the second standard comprises a peripheral componentinterconnect (PCI) standard.
 43. The electronic device of claim 19,wherein the controller is further configured to determine whether theelectronic device is capable of entering into the one mode of the powersaving modes associated with the first standard.
 44. The electronicdevice of claim 19, wherein the first standard comprises a standard thatis compatible with the second standard.
 45. A method of controlling apower consumption of an electronic device, the method being performed bya controller comprising a first interface circuit and a second interfacecircuit, the first interface circuit being adapted to interface with asecond electronic device via a serial interface using a first standardfor a serial ATA interface, the controller being coupled with thenonvolatile memory via the second interface circuit, the methodcomprising: receiving a first indicator from the second electronicdevice via the serial interface, the first indicator being an indicatorassociated with a second standard for an ATA interface being adapted tocause a reduction of a power consumption of the electronic device;responsive to receiving the first indicator, transmitting a firstresponse to the second electronic device via the serial interface; andcausing the serial interface of the electronic device to enter into onemode of power saving modes associated with the first standard, after afirst time period following the transmission of the first response. 46.The method of claim 45, further comprising: causing the serial interfaceof the electronic device to transition from the one mode of the powersave modes associated with the first standard to a second mode of thepower save modes associated with the first standard, after a second timeperiod following the transmission of the first response.
 47. The methodof claim 46, further comprising: receiving a second indicator from thesecond electronic device via the serial interface; after receiving thesecond indicator, causing the electronic device to transition from thesecond mode of the power save modes associated with the first standardto the one mode of the power save modes associated with the firststandard, after a second time period following the receipt of the secondindicator.
 48. The method of claim 47, wherein a duration of the secondtime period relates to the transitioning from the second mode of thepower save modes associated with the first standard to the one mode ofthe power save modes associated with the first standard.
 49. The methodof claim 47, wherein the second indicator relates to a check powercommand.
 50. The method of claim 46, wherein a duration of the secondtime period relates to the transitioning from the one mode of the powersave modes associated with the first standard to the second mode of thepower save modes associated with the first standard.
 51. The method ofclaim 45, wherein the first indicator relates to a first power-savecommand.
 52. The method of claim 51, wherein the first power-savecommand comprises at least one of: a Sleep command, an Idle command, aStandby command, and a Standby Immediate command under an ATA Standard;wherein the first standard comprises a Serial ATA standard; and whereinthe one mode of the power saving modes comprises Slumber Mode, PartialMode, or Idle Mode under the Serial ATA standard.
 53. The method ofclaim 52, wherein the one mode of the power saving modes comprisesSlumber Mode, Partial Mode, or Idle Mode under the Serial ATA standardif the first power-save command comprises at least one of: a Sleepcommand, an Idle command, a Standby command, and a Standby Immediatecommand under an ATA Standard.
 54. The method of claim 52, wherein theelectronic device enters into the one mode of the power saving modesafter the first time period following the transmission of the responseif the first power-save command comprises at least one of: a Sleepcommand, an Idle command, a Standby command, and a Standby Immediatecommand under an ATA Standard.
 55. The method of claim 52, wherein theprocess of receiving an indicator is repeated in response to a secondindicator.
 56. The method of claim 51, wherein the first standardcomprises a Serial ATA standard, the second standard comprises an ATAstandard, and the first power-save command comprises a command under theATA Standard.
 57. The method of claim 51, wherein the one mode of thepower saving modes is based on information included in the firstpower-save command.
 58. The method of claim 45, wherein a duration ofthe first time period relates to a frequency of receiving a plurality ofindicators including the first indicator.
 59. The method of claim 45further comprising: without receiving a second indicator subsequent tothe first indicator within the first time period, causing the electronicdevice to transition from the one mode of the power save modesassociated with the first standard to a second mode of the power savemodes associated with the first standard.
 60. The method of claim 45,wherein the electronic device is caused to enter into the one mode ofpower saving modes associated with the first standard after the firsttime period following the transmission of the first response and withoutreceiving another indicator from the second electronic device during thefirst time period.
 61. The method of claim 45, further comprising:without receiving a second indicator associated with the first standardand subsequent to the first indicator within the first time period,causing the electronic device to transition from the one mode of thepower save modes associated with the first standard to a second mode ofthe rower save modes associated with the first standard.
 62. The methodof claim 45, wherein the first standard comprises a Serial ATA standard.63. The method of claim 45, wherein the one mode of the power savingmodes comprises a Slumber Mode under a Serial ATA standard.
 64. Themethod of claim 45, wherein the second standard comprises a peripheralcomponent interconnect (PCI) standard.
 65. The method of claim 45,further comprising: determining whether the electronic device is capableof entering into the one mode of the power saving modes associated withthe first standard.
 66. The method of claim 45, wherein the firststandard comprises a standard that is compatible with the secondstandard.
 67. A non-transitory computer-readable storage medium havingstored therein a set of instructions that, when executed by at least oneprocessor of a controller, causes the controller to perform a method forcontrolling a power consumption of an electronic device, the controllercomprising a first interface circuit and a second interface circuit, thefirst interface circuit being adapted to interface with a secondelectronic device via a serial interface using a first standard for aserial ATA interface, the controller being coupled with the nonvolatilememory via the second interface circuit, the method comprising:responsive to determining that a first indicator is received from thesecond electronic device via the serial interface, the first indicatorbeing an indicator associated with a second standard for an ATAinterface being adapted to cause a reduction of a power consumption ofthe electronic device, transmitting a first response to the secondelectronic device via the serial interface; and causing the serialinterface of the electronic device to enter into one mode of powersaving modes associated with the first standard, after a first timeperiod following the transmission of the first response.
 68. The mediumof claim 67, wherein the set of instructions that is executable by theat least one processor of the controller causes the controller tofurther perform: causing the serial interface of the electronic deviceto transition from the one mode of the power save modes associated withthe first standard to a second mode of the power save modes associatedwith the first standard, after a second time period following thetransmission of the first response.
 69. The medium of claim 68, whereinthe set of instructions that is executable by the at least one processorof the controller causes the controller to further perform: receiving asecond indicator from the second electronic device via the serialinterface; after receiving the second indicator, causing the electronicdevice to transition from the second mode of the power save modesassociated with the first standard to the one mode of the power savemodes associated with the first standard, after a second time periodfollowing the receipt of the second indicator.
 70. The medium of claim69, wherein a duration of the second time period relates to thetransitioning from the second mode of the power save modes associatedwith the first standard to the one mode of the power save modesassociated with the first standard.
 71. The medium of claim 68, whereina duration of the second time period relates to the transitioning fromthe one mode of the power save modes associated with the first standardto the second mode of the power save modes associated with the firststandard.
 72. The medium of claim 67, wherein the first indicatorrelates to a first power-save command.
 73. The medium of claim 72,wherein the first power-save command comprises at least one of: a Sleepcommand, an Idle command, a Standby command, and a Standby Immediatecommand under an ATA Standard; wherein the first standard comprises aSerial ATA standard; and wherein the one mode of the power saving modescomprises Slumber Mode, Partial Mode, or Idle Mode under the Serial ATAstandard.
 74. The medium of claim 73, wherein the one mode of the powersaving modes comprises Slumber Mode, Partial Mode, or Idle Mode underthe Serial ATA standard if the first power-save command comprises atleast one of: a Sleep command, an Idle command, a Standby command, and aStandby Immediate command under an ATA Standard.
 75. The medium of claim73, wherein the electronic device enters into the one mode of the powersaving modes after the first time period following the transmission ofthe response if the first power-save command comprises at least one of:a Sleep command, an Idle command, a Standby command, and a StandbyImmediate command under an ATA Standard.
 76. The medium of claim 67,wherein the set of instructions that is executable by the at least oneprocessor of the controller to cause the controller to further perform:repeat the process of receiving an indicator in response to a secondindicator.
 77. The medium of claim 67, wherein a duration of the firsttime period relates to a frequency of receiving a plurality ofindicators including the first indicator.
 78. The medium of claim 65,wherein the set of instructions that is executable by the at least oneprocessor of the controller causes the controller to further perform:without receiving a second indicator associated with the first standardand subsequent to the first indicator within the first time period,causing the electronic device to transition from the one mode of thepower save modes associated with the first standard to a second mode ofthe power save modes associated with the first standard.
 79. The mediumof claim 67, wherein the electronic device is caused to enter into theone mode of power saving modes associated with the first standard afterthe first time period following the transmission of the first responseand without receiving another indicator from the second electronicdevice during the first time period.
 80. The medium of claim 67, whereinthe set of instructions that is executable by the at least one processorof the controller causes the controller to further perform: withoutreceiving a second indicator associated with the first standard andsubsequent to the first indicator within the first dine period, causingthe electronic device to transition from the one mode of the power savemodes associated with the first standard to a second mode of the powersave modes associated with the first standard.